I’m delighted to announce that the book “Many-Core Computing: Hardware and Software” has been published today by the Institution of Engineering and Technology (IET). I, along with Dr. Andrew Anderson, Dr. YuanWen, Barbara Barabasz, Kaveena Persand, Dr. Aravind Vasudevan, and Dr. David Gregg have written chapter 6 entitled “Hardware and software performance in deep learning”. […]
And that’s the PASM paper presented. Lots of interest and very good questions from the audience and the session chair Luca Fanucci (Università di Pisa @Unipisa). Thoroughly enjoyed it. #HiPEAC19#hipeac2019
Come and see my talk at HiPEAC 2019 about my second PhD published paper.
Convolutional neural networks (CNNs) are one of the most successful machine learning techniques for image, voice and video processing. CNNs require large amounts of processing capacity and memory bandwidth. Hardware accelerators have been proposed for CNNs which typically contain large numbers of multiply-accumulate (MAC) units, the multipliers of which are large in an integrated circuit (IC) gate count and power consumption. “Weight sharing” accelerators have been proposed where the full range of weight values in a trained CNN are compressed and put into bins and the bin index used to access the weight-shared value. We reduce power and area of the CNN by implementing parallel accumulate shared MAC (PASM) in a weight shared CNN. PASM re-architects the MAC to instead count the frequency of each weight and place it in a bin. The accumulated value is computed in a subsequent multiply phase, significantly reducing gate count and power consumption of the CNN. In this paper, we implement PASM in a weight-shared CNN convolution hardware accelerator and analyze its effectiveness. Experiments show that for a clock speed 1GHz implemented on a 45nm ASIC process our approach results in fewer gates, smaller logic, and reduced power with only a slight increase in latency. We also show that the same weight-shared-with-PASM CNN accelerator can be implemented in resource-constrained FPGAs, where the FPGA has limited numbers of digital signal processor (DSP) units to accelerate the MAC operations.
I undertook my Ph.D. Confirmation viva voce today (6th Feb 2018). This entailed a presentation and a report to two professors, Dr. Jonathan Dukes (presentation chair) and Dr. Michael Manzke (domain expert) of Trinity College Dublin who questioned me during and after the presentation. After a short discussion with my supervisor Dr. David Gregg, they […]
Dr. David Gregg and I have had my first paper of my PhD, entitled “Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks” published. The IEEE Computer Architecture Letters published it on 23 January 2017. Whilst waiting for the printed version, the IEEE has published it on their on-line pre-print server. It can also be found […]
Dr. David Gregg and I have had my first PhD paper accepted by the the pre-print server arXiv (pronounced archive). The paper, entitled “Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks” is a 4 page paper, the PDF for which can be found by searching arxiv.org and directly at Comments welcome!